Senior Design Verification Engineer
eInfochips is hiring a Senior Design Verification Engineer for their semiconductor practice. The role focuses on IP/SoC verification, including testbench architecture and coverage closure. Candidates must have strong proficiency in SystemVerilog, UVM, and industry-standard verification tools. The role requires professional experience in test planning and scripting for complex SoC environments.
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Experience
5-15 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
eInfochips is hiring a Senior Design Verification Engineer for their semiconductor practice. The role focuses on IP/SoC verification, including testbench architecture and coverage closure. Candidates must have strong proficiency in SystemVerilog, UVM, and industry-standard verification tools. The role requires professional experience in test planning and scripting for complex SoC environments.
TAL's take
Solid tier-2 engineering role with clear, technical responsibilities in the semiconductor domain.
The JD provides a very clear, specific stack and set of professional responsibilities for a verification engineer.
Salaries at eInfochips
37.5 LPA average
Based on 9 Grapevine salary entries for eInfochips.
Engineering
4 - 6 years
15 LPA average
Range: 15 - 15 LPA
Engineering
6 - 8 years
11 LPA average
Range: 11 - 11 LPA
Engineering
10 - 12 years | 13
25 LPA average
Range: 25 - 25 LPA
Product Management
0 - 2 years | L1
200 LPA average
Range: 200 - 200 LPA
Must haves
- Strong in SystemVerilog & UVM testbench development
- Experienced in IP/SoC verification and testbench architecture
- Proficient in scripting (Python/Perl/Shell)
- Hands-on with verification tools (IUS, VCS, Questa, Verdi)
- Skilled in test plans & test case design
Tools and skills
Nice to have: c, c++, gls, low-power verification, axi, ahb, chi, pcie, ddr, ethernet.
About the company
Established engineering services and product design company owned by Arrow Electronics.