Senior Design Verification Engineer

Altera is seeking a Senior Design Verification Engineer to develop verification environments for FPGA acceleration hardware. The role involves creating UVM-based testbenches, implementing coverage-driven verification, and automating flows using scripting languages. Candidates will collaborate with architecture teams to define test plans and verify complex IP specifications. This is a technical, hands-on IC role focused on high-performance semiconductor design.

• 9+ years experience in ASIC or FPGA design verification
• Expertise in Verilog or VHDL
• Strong hands-on experience in UVM-based testbenches
• Proficiency in coverage-driven and assertion-based verification
• Strong scripting skills in Python, Perl, or Tcl

Nice to have: amba, axi, ace, chi, apb, pcie, ethernet.

Altera is a well-established semiconductor company, now an independent business unit under Intel, fitting the criteria for a Tier 2 product company.