Senior / Staff Design Verification Engineer
SiFive is hiring a Senior Design Verification Engineer to join their silicon engineering team in India. The role involves managing the full verification lifecycle, from scoping and test plan creation to environment development and coverage closure for complex SoCs. Candidates must demonstrate deep expertise in SystemVerilog, UVM, and digital logic design. The position offers the opportunity to work on cutting-edge RISC-V compute platforms with a focus on high-performance applications.
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Experience
5+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
SiFive is hiring a Senior Design Verification Engineer to join their silicon engineering team in India. The role involves managing the full verification lifecycle, from scoping and test plan creation to environment development and coverage closure for complex SoCs. Candidates must demonstrate deep expertise in SystemVerilog, UVM, and digital logic design. The position offers the opportunity to work on cutting-edge RISC-V compute platforms with a focus on high-performance applications.
TAL's take
High-impact work in semiconductor engineering at a reputable, domain-specialized company with clearly defined technical requirements.
The JD provides a very clear, scoped description of verification responsibilities, required methodology (UVM/SV), and technical stack.
Must haves
- 5+ years of ASIC/SoC Design Verification experience
- Advanced proficiency in SystemVerilog (SV)
- Extensive experience with UVM methodology
- Ability to architect comprehensive verification plans
- Experience with functional coverage and code coverage closure
- Strong understanding of digital logic and computer architecture
Tools and skills
Nice to have: axi, ahb, apb, pcie, nvme, usb, ethernet.
About the company
Established semiconductor company and pioneer in RISC-V, though not a top-tier FAANG/Global unicorn.