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All jobsOnsiteEngineeringsemiconductor8-16 yearsverilog
OnsiteSeniorsemiconductor

Immediate hiring for Senior RTL design Engineers for HYD & BLR location

Modernize Chip Solutionsmulti, Telangana, IndiaPosted 20 May 2026

Modernize Chip Solutions is seeking a Senior RTL Design Engineer to work from their Hyderabad or Bengaluru offices. The role focuses on RTL logic design, verification, synthesis, and timing closure for complex SoC projects. Candidates are required to have extensive experience with various interface protocols and FPGA-based emulation platforms like HAPS or Veloce. The position requires strong scripting skills and previous experience in a full chip tapeout cycle.

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Experience

8-16 years

Function

Engineering

Work mode

Onsite, India

Company

Tier 2

What you will work on

Modernize Chip Solutions is seeking a Senior RTL Design Engineer to work from their Hyderabad or Bengaluru offices. The role focuses on RTL logic design, verification, synthesis, and timing closure for complex SoC projects. Candidates are required to have extensive experience with various interface protocols and FPGA-based emulation platforms like HAPS or Veloce. The position requires strong scripting skills and previous experience in a full chip tapeout cycle.

TAL's take

Quality 50/1005/5 clarityTier 2 company

Tier 2 company with a well-defined, specific technical role in the semiconductor domain.

Very clear expectations, specific protocol requirements, and tangible hardware emulation experience defined.

Must haves

  • 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization
  • Proficient in writing micro-architecture specifications
  • Expertise in Verilog and SoC integration
  • Experience with interface protocols like PCIe, USB, Ethernet, or DDR
  • Experience in design bring up and debug on FPGA emulation platforms
  • Fluency with scripting languages like Perl or Python
  • Must have gone through at least one tapeout

Tools and skills

verilogrtl logic designverificationsynthesistiming optimizationsoc integrationpcieusbethernetddr3/4lpddri2c/i3cspisd/sdio/emmcuarthapsveloceperlpython

Nice to have: silicon bring-up, debug.

About the company

Unfamiliar company, default mid-tier assigned.