Technical Lead II - VLSI
Ust is hiring an experienced technical lead for their VLSI verification team, specializing in top-level SoC verification. The role involves defining verification strategies, leading complex PCIe and DDR subsystem validation, and mentoring junior engineers. Candidates must have 10+ years of experience with UVM and SystemVerilog environments. This position focuses on driving end-to-end silicon quality through robust functional and coverage-based verification.
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Experience
10+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Ust is hiring an experienced technical lead for their VLSI verification team, specializing in top-level SoC verification. The role involves defining verification strategies, leading complex PCIe and DDR subsystem validation, and mentoring junior engineers. Candidates must have 10+ years of experience with UVM and SystemVerilog environments. This position focuses on driving end-to-end silicon quality through robust functional and coverage-based verification.
TAL's take
Solid senior-level technical lead role in the semiconductor domain with clear expectations, despite being at a tier-2 service-oriented company.
The JD clearly defines the technical domain, core protocols (PCIe, DDR), methodology (UVM/SystemVerilog), and responsibilities.
Salaries at Ust
20.9 LPA average
Based on 19 Grapevine salary entries for Ust.
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Must haves
- 10+ years of experience in SoC verification
- Strong expertise in full-chip verification
- Hands-on experience with PCIe and DDR verification
- Proficiency in SystemVerilog and UVM
- Experience with simulation, debugging, and coverage analysis tools
Tools and skills
About the company
Ust is an established IT services and consulting firm; default mid-tier assigned.
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