SMTS-Design Verification Engineer: SOC Focused
Tsavorite Scalable Intelligence is a silicon startup developing agentic silicon for AI applications. The role focuses on end-to-end data-path verification for high-performance ARM-based SoCs, including PCIe and CXL fabrics. Candidates must be proficient in SystemVerilog, UVM, and possess deep knowledge of cache coherency and UCIe protocols. The position involves verifying multi-chiplet systems and collaborating with architecture and firmware teams.
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Experience
11-14 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Tsavorite Scalable Intelligence is a silicon startup developing agentic silicon for AI applications. The role focuses on end-to-end data-path verification for high-performance ARM-based SoCs, including PCIe and CXL fabrics. Candidates must be proficient in SystemVerilog, UVM, and possess deep knowledge of cache coherency and UCIe protocols. The position involves verifying multi-chiplet systems and collaborating with architecture and firmware teams.
TAL's take
High-impact role in a specialized semiconductor startup, clear domain focus, though the company is very early-stage.
Highly specific technical requirements for SoC verification in an agentic silicon context.
Must haves
- UCIe system knowledge
- Understanding of cache coherency
- Proficiency in SystemVerilog and UVM
- Transaction-level verification experience
Tools and skills
Nice to have: multi-chip system experience, real workloads, chi, ace.
About the company
Newly founded AI hardware startup with experienced industry team, currently below established tier 1 unicorn status.