Application Specific Integrated Circuit Design Engineer
MBR Partners is seeking a Senior ASIC Design Engineer to own end-to-end design for AI ASIC subsystems. The role involves architectural trade-offs, RTL development, timing closure, and silicon validation for high-performance AI workloads. Candidates must have extensive experience with the full chip development lifecycle, including IP integration, power/clock management, and DFT. This is a technical IC role focused on producing high-quality RTL for production silicon.
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Experience
7+ years
Function
Engineering
Work mode
Onsite, United Arab Emirates
Company
Tier 3
What you will work on
MBR Partners is seeking a Senior ASIC Design Engineer to own end-to-end design for AI ASIC subsystems. The role involves architectural trade-offs, RTL development, timing closure, and silicon validation for high-performance AI workloads. Candidates must have extensive experience with the full chip development lifecycle, including IP integration, power/clock management, and DFT. This is a technical IC role focused on producing high-quality RTL for production silicon.
TAL's take
Unclear company context as it appears to be a recruitment firm rather than a direct tech employer.
The JD is extremely detailed regarding the ASIC design flow, technical stack, and specific subsystem responsibilities.
Must haves
- 7+ years experience in RTL design and ASIC development
- Proficiency in Verilog/SystemVerilog
- Experience in IP integration for CPUs, NoCs, GPUs/NPUs, or high-speed interfaces
- Deep understanding of clock domains and asynchronous interfaces
- Experience with formal equivalency checking and DFT implementation
- Experience writing specifications and SDC constraints for timing closure
Tools and skills
Nice to have: python, hbm, gddr.
About the company
Small recruitment or consultancy firm, not a direct semiconductor product company.