Senior Design Verification Engineer
Scaledge Technology is seeking a Senior Design Verification Engineer in the semiconductor domain. The role involves building test environments, defining verification plans, and driving coverage closure for high-speed protocols. Candidates must be proficient in System Verilog and UVM. The position requires strong analytical and debugging capabilities for end-to-end project execution.
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Experience
Experience not specified
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Scaledge Technology is seeking a Senior Design Verification Engineer in the semiconductor domain. The role involves building test environments, defining verification plans, and driving coverage closure for high-speed protocols. Candidates must be proficient in System Verilog and UVM. The position requires strong analytical and debugging capabilities for end-to-end project execution.
TAL's take
Solid technical role in semiconductor domain but company profile and YOE requirements are not explicitly detailed.
Clear technical requirements and responsibilities, though slightly broad on the protocol requirements.
Must haves
- Proficiency in System Verilog and UVM
- Ability to build test cases and environments
- Experience with at least one high speed protocol
- Strong analytical and debugging skills
- Experience defining verification plans
- Developing UVM test benches and driving coverage closure
Tools and skills
About the company
Unfamiliar company, default mid-tier.