CAD/Methodology Physical Design Team Lead
Cisco is looking for a Physical Design Team Lead to join the Silicon One group in Bengaluru. You will oversee CAD methodology and flow development from RTL to GDS for complex network devices. The role requires extensive experience in PnR, signoff methodologies, and automation using Python and TCL. You will lead a technical team and drive innovation in high-quality VLSI design workflows.
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Experience
10+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 1
What you will work on
Cisco is looking for a Physical Design Team Lead to join the Silicon One group in Bengaluru. You will oversee CAD methodology and flow development from RTL to GDS for complex network devices. The role requires extensive experience in PnR, signoff methodologies, and automation using Python and TCL. You will lead a technical team and drive innovation in high-quality VLSI design workflows.
TAL's take
High-impact role at a Tier 1 global company working on cutting-edge silicon architecture with clear technical leadership requirements.
The JD provides a very clear definition of the team, the technical focus (CAD/Physical Design), and specific tools and methodologies required.
Salaries at Cisco
23.8 LPA average
Based on 683 Grapevine salary entries for Cisco.
Engineering
0 - 2 years | G4
15 LPA average
Range: 10 - 20 LPA
Engineering
2 - 4 years | G6
17 LPA average
Range: 9 - 26 LPA
Engineering
4 - 6 years | G8
20 LPA average
Range: 9 - 30 LPA
Engineering
6 - 8 years | G8
24 LPA average
Range: 13 - 43 LPA
Must haves
- BSc/MSc in Electrical or Computer Engineering
- 10+ years of experience
- Expertise in PnR and Signoff methodologies
- Proficiency with industry-standard tools
- Strong scripting experience in TCL and Python
- Experience with large-scale SoC programs
- Prior management experience
Tools and skills
Nice to have: networking asic design, low latency, high-throughput clocking, serdes, packet processors.
About the company
Cisco is a major global technology company and a well-recognized leader in networking and silicon infrastructure.
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