Principal Product Engineer – Digital & Signoff Group (DSG)
Cadence is seeking a Principal Product Engineer for the Digital & Signoff Group in Bengaluru. This role bridges R&D, application engineering, and customer needs to advance chip design software for advanced nodes. Responsibilities include diagnosing software issues, benchmarking PPA, and developing RTL-to-GDSII methodologies. Candidates must have extensive experience in physical design and EDA tool proficiency.
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Experience
4+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Cadence is seeking a Principal Product Engineer for the Digital & Signoff Group in Bengaluru. This role bridges R&D, application engineering, and customer needs to advance chip design software for advanced nodes. Responsibilities include diagnosing software issues, benchmarking PPA, and developing RTL-to-GDSII methodologies. Candidates must have extensive experience in physical design and EDA tool proficiency.
TAL's take
Strong, well-defined role in a leading EDA company with clear scope in high-impact chip design software.
The JD provides a very clear scope, responsibilities, and technical requirements specific to the digital implementation domain.
Must haves
- Bachelors in Electronics Engineering with 6+ years experience
- Masters in Electronics Engineering with 4+ years digital implementation experience
- Deep understanding of full ASIC design flow (RTL-to-GDSII)
- Hands-on experience with timing closure and PPA optimization at 7nm, 5nm or below
- High familiarity with industry-standard EDA tools
- Proficiency in Tcl, Python, or Perl
Tools and skills
Nice to have: ai-driven productivity tools.
About the company
Cadence is a major established player in the EDA software industry.
Posts mentioning Cadence
Looking for referrals - VLSI Engineer roles
Hello everyone! I'm actively looking for new opportunities in VLSI related companies. I have 1 year of experience at IIT Madras, where I have worked in Analog RFIC SoC design using 65nm CMOS tech, analog layout design, DRC, LVS, PEX, EMX, test bench, performance verification, Hardware RFIC SoC verification using FPGA and Embedded boards, verilog HDL, VHDL, python. Through these roles, I have developed skills in FPGA programming, verilog HDL RTL coding, Python, Embedded programming, Cadence layout and schematic analysis and performance verification. If you guys have any openings in your company, I request you to please provide me a refferal. Reach me out at srinathsri.b@gmail.com for more details. Looking forward to hearing from you all. Thank you
300+ Companies paying 12LPA+ base for SDE-1 role in India
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Hello,
I have an SDE @Samsung with 1+ YOE and serving notice period. My offer with Cadence is getting delayed by 3 months. My notice period ends in mid December. Any leads for SDE roles would be appreciated. Thank you