Sr. Design Engineer 1
Tessolve is seeking a Senior Verification Engineer to join their semiconductor engineering team. You will be responsible for developing IP and SoC verification environments using SystemVerilog and UVM, validating protocols, and driving coverage closure. The role requires strong expertise in bus protocols, scripting for automation, and technical documentation. This position provides an opportunity to work on complex silicon designs within a global team environment.
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Experience
5-15 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Tessolve is seeking a Senior Verification Engineer to join their semiconductor engineering team. You will be responsible for developing IP and SoC verification environments using SystemVerilog and UVM, validating protocols, and driving coverage closure. The role requires strong expertise in bus protocols, scripting for automation, and technical documentation. This position provides an opportunity to work on complex silicon designs within a global team environment.
TAL's take
Solid established mid-stage semiconductor services company with clear, well-defined technical scope for a senior verification role.
Very clear and well-structured JD with specific technical requirements, responsibilities, and domain focus.
Must haves
- 5-15 years of experience in IP and SoC verification
- Proficiency in SystemVerilog and UVM
- Experience with AHB, AXI, APB bus protocols
- Strong scripting skills in Python, Perl, Shell, or TCL
- Ability to drive coverage closure
Tools and skills
Nice to have: pcie, usb, mipi, upf, ddr, synopsys vcs, cadence incisive.
About the company
Established global semiconductor design services company with significant scale and industry footprint.