Lead Product Engineer - MIPI Protocol
Cadence is hiring a Lead Product Engineer to drive the adoption of Verification IP (VIP) for MIPI protocols at top-tier customer accounts. The role involves high-level technical support, product definition based on customer needs, and knowledge transfer to field engineering teams. Candidates must have extensive experience in design and verification, specifically using System Verilog and UVM. This position requires a collaborative mindset and the ability to lead complex cross-functional programs.
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Experience
7-12 years
Function
Engineering
Work mode
Hybrid, India
Company
Tier 2
What you will work on
Cadence is hiring a Lead Product Engineer to drive the adoption of Verification IP (VIP) for MIPI protocols at top-tier customer accounts. The role involves high-level technical support, product definition based on customer needs, and knowledge transfer to field engineering teams. Candidates must have extensive experience in design and verification, specifically using System Verilog and UVM. This position requires a collaborative mindset and the ability to lead complex cross-functional programs.
TAL's take
Senior-level specialized engineering role at a major global electronic design automation company with clear ownership and project leadership.
Well-defined role with specific protocol expertise required and clear responsibilities in pre-sales, product definition, and team leadership.
Must haves
- 7-12 years of experience with Verification and Design
- Working knowledge with MIPI (CSI2/DSI/I3C/PHY) protocols
- Experience developing verification environments using System Verilog
- Working knowledge and experience with the UVM methodology
- Excellent problem-solving and debugging skills
Tools and skills
About the company
Cadence is a well-established EDA software company, falling under Tier 2 for general engineering roles compared to pure-play tech unicorns.
Posts mentioning Cadence
Looking for referrals - VLSI Engineer roles
Hello everyone! I'm actively looking for new opportunities in VLSI related companies. I have 1 year of experience at IIT Madras, where I have worked in Analog RFIC SoC design using 65nm CMOS tech, analog layout design, DRC, LVS, PEX, EMX, test bench, performance verification, Hardware RFIC SoC verification using FPGA and Embedded boards, verilog HDL, VHDL, python. Through these roles, I have developed skills in FPGA programming, verilog HDL RTL coding, Python, Embedded programming, Cadence layout and schematic analysis and performance verification. If you guys have any openings in your company, I request you to please provide me a refferal. Reach me out at srinathsri.b@gmail.com for more details. Looking forward to hearing from you all. Thank you
300+ Companies paying 12LPA+ base for SDE-1 role in India
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Hello,
I have an SDE @Samsung with 1+ YOE and serving notice period. My offer with Cadence is getting delayed by 3 months. My notice period ends in mid December. Any leads for SDE roles would be appreciated. Thank you