Principal AI Chip Design Engineer(SG)

Canaan Inc. is seeking a Principal AI Chip Design Engineer to lead RTL design for AI chip SoC and subsystems. The role involves defining microarchitecture, leading SoC integration, and working across verification and physical design teams. Candidates require 8+ years of experience in complex ASIC design flows and strong Verilog/SystemVerilog proficiency. The position requires deep expertise in SoC components like NoC, DMA, and memory subsystems.

• 8+ years of experience in SoC or RTL design
• Strong Verilog/SystemVerilog RTL coding skills
• Deep understanding of SoC architecture (AXI/AHB/APB, NoC, DMA)
• Familiarity with ASIC design flow (lint, CDC/RDC, synthesis, STA)
• Experience in SoC/IP integration and top-level RTL design

Nice to have: ai accelerator, npu, gpu, cpu, dsp.

Publicly traded company specializing in blockchain hardware and AI chips with established industry presence.