CPU Verification Engineer
Scaledge Technology is seeking a Senior Design Verification Engineer to work in the semiconductor domain. The role involves building UVM verification environments from scratch and driving coverage closure for complex silicon designs. Candidates are expected to possess strong hands-on expertise in SystemVerilog and UVM, with focus areas in IOMMU or Functional Safety. This position offers exposure to advanced compute systems and safety-critical hardware development.
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Experience
5-8 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Scaledge Technology is seeking a Senior Design Verification Engineer to work in the semiconductor domain. The role involves building UVM verification environments from scratch and driving coverage closure for complex silicon designs. Candidates are expected to possess strong hands-on expertise in SystemVerilog and UVM, with focus areas in IOMMU or Functional Safety. This position offers exposure to advanced compute systems and safety-critical hardware development.
TAL's take
Solid tier-2 hardware engineering role with well-defined technical scope in verification.
Highly specific JD focusing on UVM verification environments, IOMMU, and functional safety.
Must haves
- 5-8 years of experience in Design Verification
- Strong hands-on expertise in SystemVerilog and UVM methodology
- Proven ability to build verification environments from scratch
- Excellent debugging and analytical skills with ownership mindset
Tools and skills
Nice to have: iommu, smmu, memory management units, amba, axi, chi, c, c++, iso 26262, fault injection.
About the company
unfamiliar company, default mid-tier