Silicon Senior uArch/RTL Engineer, Google Cloud
Google is seeking a Senior Silicon uArch/RTL Engineer to drive TPU technology for large-scale AI/ML data center applications. You will own microarchitecture and RTL implementation for complex IPs, while collaborating with verification and physical design teams. The role requires deep expertise in ASIC/SoC design flows, Verilog, and hardware performance optimization. This position focuses on the design of critical infrastructure powering Google's AI capabilities.
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Experience
8+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 1
What you will work on
Google is seeking a Senior Silicon uArch/RTL Engineer to drive TPU technology for large-scale AI/ML data center applications. You will own microarchitecture and RTL implementation for complex IPs, while collaborating with verification and physical design teams. The role requires deep expertise in ASIC/SoC design flows, Verilog, and hardware performance optimization. This position focuses on the design of critical infrastructure powering Google's AI capabilities.
TAL's take
Role at Google working on TPU hardware acceleration, offering significant technical impact and high visibility.
Very clear responsibilities focused on microarchitecture, RTL implementation, and design verification for TPU hardware.
Salaries at Google
33.6 LPA average
Based on 998 Grapevine salary entries for Google.
Engineering
0 - 2 years | L1
16 LPA average
Range: 2 - 30 LPA
Engineering
2 - 4 years | L4
24 LPA average
Range: 0 - 100 LPA
Engineering
4 - 6 years | L4
28 LPA average
Range: 0 - 90 LPA
Engineering
6 - 8 years | L4
44 LPA average
Range: 10 - 69 LPA
Must haves
- 8 years of experience in ASIC/SoC development
- Proficiency with Verilog/SystemVerilog
- Experience in micro-architecture design of IPs and Subsystems
- Experience in design verification, synthesis, and timing/power analysis
- Bachelor's degree in Electrical or Computer Engineering
Tools and skills
Nice to have: python, c/c++, perl, soc designs, integration flows, processor design, accelerators, bus architectures, noc, memory hierarchies.
About the company
Global tier-1 technology company.