STA Engineer
AMD is seeking a Silicon Design Engineer 2 to join their team in Bengaluru for timing closure of high-frequency blocks and subsystems. The role focuses on driving pre-route timing checks, SDC constraint management, and ECO implementation using EDA tools. Candidates must have expertise in STA, SDC methodologies, and Tcl scripting to ensure quality design handoffs. This position offers the opportunity to contribute to next-generation computing and AI hardware systems.
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Experience
3+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 1
What you will work on
AMD is seeking a Silicon Design Engineer 2 to join their team in Bengaluru for timing closure of high-frequency blocks and subsystems. The role focuses on driving pre-route timing checks, SDC constraint management, and ECO implementation using EDA tools. Candidates must have expertise in STA, SDC methodologies, and Tcl scripting to ensure quality design handoffs. This position offers the opportunity to contribute to next-generation computing and AI hardware systems.
TAL's take
Tier-1 company with a clearly defined technical role in silicon design engineering.
The JD provides specific responsibilities and required technical competencies related to timing signoff and EDA tools.
Salaries at AMD
45.7 LPA average
Based on 3 Grapevine salary entries for AMD.
Other roles
2 - 4 years
20 LPA average
Range: 20 - 20 LPA
Other roles
12 - 14 years
76 LPA average
Range: 76 - 76 LPA
Other roles
16 - 18 years
41 LPA average
Range: 41 - 41 LPA
Must haves
- 3+ years experience for timing closure of block/SS
- Well versed with timing signoff methodology and corner definitions
- Mix of SDC knowledge and EDA timing tool competence
- Tcl based scripting capability
- Experience analyzing timing reports and identifying design issues
Tools and skills
Nice to have: synopsys design compiler, primetime, spyglass, fishtail, tweaker.
About the company
AMD is a globally recognized semiconductor company.
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