Lead Silicon Design Engineer - RTL
AMD is seeking a Lead Silicon Design Engineer to join their IP design team in Hyderabad. The role involves developing synthesizable RTL for IP cores, contributing to design specifications, and ensuring high-quality synthesis and timing closure. You will collaborate with verification, architecture, and physical design teams while mentoring junior staff. Successful candidates must have at least 8 years of RTL design experience and proficiency with industry-standard ASIC design flows.
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Experience
8+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 1
What you will work on
AMD is seeking a Lead Silicon Design Engineer to join their IP design team in Hyderabad. The role involves developing synthesizable RTL for IP cores, contributing to design specifications, and ensuring high-quality synthesis and timing closure. You will collaborate with verification, architecture, and physical design teams while mentoring junior staff. Successful candidates must have at least 8 years of RTL design experience and proficiency with industry-standard ASIC design flows.
TAL's take
Lead role at a Tier 1 global semiconductor firm working on high-performance IP.
Very clear responsibilities, tech stack, and team context defined.
Salaries at AMD
45.7 LPA average
Based on 3 Grapevine salary entries for AMD.
Other roles
2 - 4 years
20 LPA average
Range: 20 - 20 LPA
Other roles
12 - 14 years
76 LPA average
Range: 76 - 76 LPA
Other roles
16 - 18 years
41 LPA average
Range: 41 - 41 LPA
Must haves
- 8 years experience in RTL ASIC design
- Proficiency in Verilog and System Verilog
- Experience with synthesis tools and timing closure
- Knowledge of AXI, AHB, AMBA protocols
- Experience with functional verification tools
- Proficiency in scripting languages like Python, Perl, or TCL
Tools and skills
Nice to have: github copilot, cursor, claude, codex, gpt, microsoft m365 copilot, chatgpt, atlassian rovo.
About the company
Global leading semiconductor company.
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