Sr. Design Engineer 2
Tessolve is hiring a Senior STA Engineer for their semiconductor and ASIC design services team. The role focuses on static timing analysis, timing sign-off, SDC constraint development, and timing ECO execution for complex SoCs. Candidates must be proficient in industry-standard tools like PrimeTime or Tempus and possess strong scripting skills for automation. The hire will collaborate across design teams to ensure timing convergence for advanced technology node projects.
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Experience
7+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Tessolve is hiring a Senior STA Engineer for their semiconductor and ASIC design services team. The role focuses on static timing analysis, timing sign-off, SDC constraint development, and timing ECO execution for complex SoCs. Candidates must be proficient in industry-standard tools like PrimeTime or Tempus and possess strong scripting skills for automation. The hire will collaborate across design teams to ensure timing convergence for advanced technology node projects.
TAL's take
Solid tier-2 role in specialized semiconductor domain with well-defined technical scope.
Extremely clear technical requirements and responsibilities for a specialized STA role.
Must haves
- Hands-on experience with STA tools like PrimeTime or Tempus
- Expertise in SDC constraints and timing sign-off
- Familiarity with MMMC timing analysis
- Proficiency in scripting with Tcl, Perl, or Python for automation
- Experience with complex SoC/ASIC designs at advanced technology nodes
Tools and skills
Nice to have: upf, library characterization, si.
About the company
Established semiconductor engineering services company with significant global scale.