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Senior Physical Design Engineer

Mulya TechnologiesBengaluru, IndiaPosted 16 May 2026

Mulya Technologies is looking for a Senior Physical Design Engineer to join their semiconductor team in Bengaluru. The role involves managing RTL to GDS implementation flows, including floor-planning, clock tree synthesis, and timing closure for complex SoCs. Candidates must be proficient in Synopsys tools such as ICC and Fusion Compiler. This position requires deep collaboration with micro-architects to optimize for performance, power, and area in sub-7nm nodes.

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Experience

Experience not specified

Function

Engineering

Work mode

Onsite, India

Company

Tier 2

What you will work on

Mulya Technologies is looking for a Senior Physical Design Engineer to join their semiconductor team in Bengaluru. The role involves managing RTL to GDS implementation flows, including floor-planning, clock tree synthesis, and timing closure for complex SoCs. Candidates must be proficient in Synopsys tools such as ICC and Fusion Compiler. This position requires deep collaboration with micro-architects to optimize for performance, power, and area in sub-7nm nodes.

TAL's take

Quality 55/1005/5 clarityTier 2 company

Solid technical role in a specialized domain, though the company status is unfamiliar.

Very clear and specific responsibilities and required toolsets for a Physical Design role.

Must haves

  • Experience in all aspects of physical design
  • Proficiency with synthesis, place & route, and STA tools
  • Experience implementing clock trees and power grids
  • Scripting for physical design flow automation
  • Experience with Synopsys tools (Design Compiler, ICC, Fusion Compiler)

Tools and skills

synthesisfloor-planningplace and routeclock tree synthesisstatic timing analysisem/irpdvsynopsys design compilerprime timeiccfusion compilersystem verilog

About the company

Unfamiliar company in the semiconductor space, defaulting to tier 2.

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