PMTS- Design Verification Engineer: PCIE / CXL Focused
Tsavorite Scalable Intelligence is seeking an experienced Design Verification Engineer to work on server-class PCIe/CXL controllers for AI silicon. The role involves developing testplans, environments, and checkers for block and SoC level verification. Candidates must have deep expertise in PCIe/CXL protocols and SV/UVM methodologies. You will work closely with architects and RTL design teams to ensure functional correctness of complex sub-systems.
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Experience
14+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Tsavorite Scalable Intelligence is seeking an experienced Design Verification Engineer to work on server-class PCIe/CXL controllers for AI silicon. The role involves developing testplans, environments, and checkers for block and SoC level verification. Candidates must have deep expertise in PCIe/CXL protocols and SV/UVM methodologies. You will work closely with architects and RTL design teams to ensure functional correctness of complex sub-systems.
TAL's take
High-impact role in an emerging AI-silicon startup with a strong engineering team, though the company is very young.
The JD provides a highly specific domain focus (PCIe/CXL), clear block-level tasks, and precise technical requirements.
Must haves
- 14+ years of relevant experience
- Strong domain knowledge in PCIe and CXL protocols
- Strong expertise with SV/UVM methodology
- 5+ years hands-on experience in IP/sub-system/SoC verification
- Experience with simulation and debug tools like Questa or VCS
Tools and skills
Nice to have: apb, axi.
About the company
Early-stage startup founded by industry veterans, strong team pedigree but limited market presence.