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Director – Pre-Silicon Verification

Alteramulti, Karnataka, IndiaPosted 19 May 2026

Altera is seeking a Director to lead their Pre-Silicon Verification IP development team. The role focuses on defining verification strategy, developing test benches, and driving coverage closure for FPGA designs. Candidates must have deep experience in System Verilog and UVM methodologies. This is a leadership position based across New Delhi and Bengaluru with hybrid potential.

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Experience

Experience not specified

Function

Engineering

Work mode

Hybrid, India

Company

Tier 2

What you will work on

Altera is seeking a Director to lead their Pre-Silicon Verification IP development team. The role focuses on defining verification strategy, developing test benches, and driving coverage closure for FPGA designs. Candidates must have deep experience in System Verilog and UVM methodologies. This is a leadership position based across New Delhi and Bengaluru with hybrid potential.

TAL's take

Quality 75/1005/5 clarityTier 2 company

High-level leadership role at an established semiconductor player with clear, technical ownership of IP development and verification strategy.

The JD provides a highly specific description of the verification lifecycle, methodology requirements, and team leadership expectations.

Must haves

  • Experience in pre-silicon validation and verification
  • Proficiency in OVM and UVM
  • Expertise in System Verilog
  • Ability to define and execute constrained random verification strategies
  • Experience leading multidisciplinary engineering teams

Tools and skills

ovmuvmsystem verilogconstrained random verification methodologies

Nice to have: fpga architecture, fpga prototyping.

About the company

Altera is a well-established hardware and semiconductor company, formerly an Intel subsidiary, representing a solid product-based engineering environment.

Posts mentioning Altera