Sr. SoC Design Verification Engineer

Altera is hiring a Senior SoC Design Verification Engineer in Bengaluru for its semiconductor division. The role involves leading design for debug architecture verification, creating test benches using UVM, and coordinating cross-functional verification plans. Candidates must have 10+ years of experience with ASIC verification and expertise in System Verilog. The role requires strong collaboration across global sites in a dynamic environment.

• 10+ years experience with complex ASIC designs or verification
• Familiarity with System Verilog
• Experience with UVM verification methodology
• Experience with formal verification method
• Working knowledge of scripting in Linux/Unix environments
• Experience with Design for Debug architecture

Nice to have: emulation, perl, python, arm, risc, ultrasoc, tessent embedded analytics.

Altera is an established semiconductor company with a significant footprint but lacks the specific Tier 1 status of the listed global tech giants.