Full Chip Physical Design Architect
LeadSoc Technologies is seeking a Full Chip Physical Design Architect in Bengaluru to define and lead methodologies for complex SoC designs. You will be responsible for end-to-end physical design, including floorplanning, timing closure, and sign-off, across advanced technology nodes. The role requires extensive experience with EDA tools and a proven track record of successful tape-outs. You will also lead design reviews and mentor engineering teams to drive technical excellence.
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Experience
12+ years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
LeadSoc Technologies is seeking a Full Chip Physical Design Architect in Bengaluru to define and lead methodologies for complex SoC designs. You will be responsible for end-to-end physical design, including floorplanning, timing closure, and sign-off, across advanced technology nodes. The role requires extensive experience with EDA tools and a proven track record of successful tape-outs. You will also lead design reviews and mentor engineering teams to drive technical excellence.
TAL's take
High-impact architect role with clear scope, though company is less recognized globally.
Highly specific technical requirements and responsibilities aligned with the architect title.
Salaries at LeadSoc Technologies Pvt Ltd
25.0 LPA average
Based on 2 Grapevine salary entries for LeadSoc Technologies Pvt Ltd.
Other roles
4 - 6 years | L1
10 LPA average
Range: 10 - 10 LPA
Other roles
6 - 8 years | L6
40 LPA average
Range: 40 - 40 LPA
Must haves
- 12+ years experience in SoC physical design
- Expertise at full-chip level
- Track record of multiple tape-outs in 7nm/5nm or below
- Deep expertise in EDA tools like Synopsys or Cadence
- Strong background in STA and power analysis
Tools and skills
Nice to have: tcl, python, perl.
About the company
Unfamiliar company, default mid-tier assigned.