Sr Design Lead-PD
Tessolve is hiring a Senior Physical Design Engineer for their semiconductor engineering team. The role focuses on end-to-end physical implementation including floorplanning, routing, timing closure, and physical verification. Candidates must be proficient in EDA tools from Cadence, Synopsys, or Mentor and be capable of handling tape-out readiness. This role involves cross-functional collaboration with RTL and verification teams to deliver manufacturable silicon designs.
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Experience
Experience not specified
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Tessolve is hiring a Senior Physical Design Engineer for their semiconductor engineering team. The role focuses on end-to-end physical implementation including floorplanning, routing, timing closure, and physical verification. Candidates must be proficient in EDA tools from Cadence, Synopsys, or Mentor and be capable of handling tape-out readiness. This role involves cross-functional collaboration with RTL and verification teams to deliver manufacturable silicon designs.
TAL's take
Solid established semiconductor services firm with clear technical requirements and defined scope.
Well-defined responsibilities centered on the physical design flow for SoCs and IP blocks.
Must haves
- Experience in floorplanning, placement, CTS, routing, and timing closure
- Proficiency in industry-standard EDA tools like Cadence, Synopsys, or Mentor
- Ability to perform DRC/LVS checks and resolve manufacturing issues
- Knowledge of power optimization and signal integrity mitigation
- Experience supporting ECO implementation and tape-out processes
Tools and skills
About the company
Established engineering services company in the semiconductor domain with global operations.