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OnsiteLeadsemiconductor

STA Lead Engineer

MediatekBengaluru, Karnataka, IndiaPosted 20 May 2026

Mediatek is seeking an STA Lead Engineer to manage timing convergence for complex multi-voltage SoC and subsystem designs in the semiconductor domain. The role involves managing timing ECOs, validating constraints, and collaborating with cross-functional physical design and synthesis teams. Candidates must have extensive experience in STA fundamentals, specifically with PrimeTime and Tempus, alongside proficiency in scripting languages like Python and TCL. This position is based in Bengaluru and focuses on high-speed design tape-outs and advanced timing optimization.

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Experience

6+ years

Function

Engineering

Work mode

Onsite, India

Company

Tier 1

What you will work on

Mediatek is seeking an STA Lead Engineer to manage timing convergence for complex multi-voltage SoC and subsystem designs in the semiconductor domain. The role involves managing timing ECOs, validating constraints, and collaborating with cross-functional physical design and synthesis teams. Candidates must have extensive experience in STA fundamentals, specifically with PrimeTime and Tempus, alongside proficiency in scripting languages like Python and TCL. This position is based in Bengaluru and focuses on high-speed design tape-outs and advanced timing optimization.

TAL's take

Quality 80/1005/5 clarityTier 1 company

High-tier semiconductor firm offering a clear technical lead role with well-defined scope.

The JD provides a very clear scope of work, technical requirements, and specific toolsets for an STA lead position.

Salaries at Mediatek

19.6 LPA average

Based on 11 Grapevine salary entries for Mediatek.

View all salaries

Engineering

0 - 2 years | L1

15 LPA average

Range: 12 - 17 LPA

Other roles

0 - 2 years | L1

14 LPA average

Range: 14 - 14 LPA

Other roles

2 - 4 years | L1

19 LPA average

Range: 15 - 22 LPA

Other roles

4 - 6 years | Senior engineer

21 LPA average

Range: 11 - 27 LPA

Must haves

  • 6+ years of relevant experience in STA and semiconductor design
  • Experience in driving timing convergence at chip-level and hard macro level
  • Expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints
  • Hands-on experience with STA tools: PrimeTime, Tempus, Tweaker
  • Familiarity with ASIC back-end flows such as ICC2 and Innovus
  • Familiar in scripting languages: TCL, Perl, and Python

Tools and skills

primetimetempustweakerstaaocv/pocvctsicc2innovustclperlpython

Nice to have: low-power synthesis, equivalence checks.

About the company

Global leading semiconductor company with strong engineering footprint.

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