Project Lead I - VLSI
This role is for a SOC Design Verification Engineer at Ust within the semiconductor domain. The engineer will join the SOC DV CPU and BUS team working across various infrastructure projects. Candidates are required to have deep expertise in Verilog, C, and ARM-based processor architectures alongside core AMBA protocols. Strong debug skills for complex NOC paths are considered a significant advantage.
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Experience
Experience not specified
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
This role is for a SOC Design Verification Engineer at Ust within the semiconductor domain. The engineer will join the SOC DV CPU and BUS team working across various infrastructure projects. Candidates are required to have deep expertise in Verilog, C, and ARM-based processor architectures alongside core AMBA protocols. Strong debug skills for complex NOC paths are considered a significant advantage.
TAL's take
Solid tier-2 role in semiconductor verification with clearly defined technical requirements and domain scope.
The role is highly specific, clearly defining the team context (CPU, BUS), required stack, and technical protocols.
Salaries at Ust
20.9 LPA average
Based on 19 Grapevine salary entries for Ust.
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6 - 8 years
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Must haves
- Understanding of ARM based Processor and Instruction set
- Proficiency in Verilog
- Proficiency in C
- Knowledge of AMBA protocols like AXI, ACE, AHB, CHI
Tools and skills
Nice to have: debug skills.
About the company
Global IT services and product engineering firm with significant engineering operations, classified as tier 2.
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