Jobs on TAL
All jobsHybridEngineeringsemiconductor8+ yearsverilog
HybridStaff/Principal/Architectsemiconductor

Senior Staff, RTL Design Engineer

Renesas ElectronicsHyderabad, Telangana, IndiaPosted 18 May 2026

Renesas Electronics is hiring a Senior Staff RTL Design Engineer to lead chip-level RTL development within their SoC team. The role focuses on designing power-efficient chips, collaborating with architecture and physical design teams, and ensuring PPA goals. Candidates must have 8+ years of relevant experience with specific expertise in RTL design and industry-standard protocols. This position is based in Hyderabad and operates under a hybrid work model.

Matched by TAL

50k new jobs listed every day. Install TAL to find more jobs like this.

Install TAL

Experience

8+ years

Function

Engineering

Work mode

Hybrid, India

Company

Tier 2

What you will work on

Renesas Electronics is hiring a Senior Staff RTL Design Engineer to lead chip-level RTL development within their SoC team. The role focuses on designing power-efficient chips, collaborating with architecture and physical design teams, and ensuring PPA goals. Candidates must have 8+ years of relevant experience with specific expertise in RTL design and industry-standard protocols. This position is based in Hyderabad and operates under a hybrid work model.

TAL's take

Quality 75/1005/5 clarityTier 2 company

High-impact senior role at a major global semiconductor firm with well-defined technical requirements.

Clear and detailed job description defining specific chip-level RTL design responsibilities and domain expertise required.

Salaries at Renesas Electronics

24.0 LPA average

Based on 2 Grapevine salary entries for Renesas Electronics.

View all salaries

Other roles

4 - 6 years

3 LPA average

Range: 3 - 3 LPA

Other roles

6 - 8 years

45 LPA average

Range: 45 - 45 LPA

Must haves

  • 8+ years of hardware engineering experience in IP/chip-level RTL design
  • Expertise in Verilog and SystemVerilog
  • Experience in D2D protocols like UCIe or Bunch-of-wires
  • Proven track record in timing closure and physically aware design flows
  • Strong understanding of synthesis, STA, and power optimization techniques

Tools and skills

verilogsystemverilogd2d protocolsuciebunch-of-wiresahbaxichimemory controllerssynthesisstapower optimization techniques

Nice to have: clocking, system modes, power management, debug, security.

About the company

Global semiconductor company, established market presence in multiple industrial verticals.

Posts mentioning Renesas Electronics