Technical Lead I - VLSI
Ust is hiring a Technical Lead in the VLSI domain to work on high-speed verification projects. The role focuses on the complete verification lifecycle, including test planning, environment development, and coverage closure. Candidates must have deep expertise in SystemVerilog, UVM, and PCIe protocols, specifically Gen5 or Gen6. This is a technical leadership position requiring strong analytical and debugging capabilities.
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Experience
5-8 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Ust is hiring a Technical Lead in the VLSI domain to work on high-speed verification projects. The role focuses on the complete verification lifecycle, including test planning, environment development, and coverage closure. Candidates must have deep expertise in SystemVerilog, UVM, and PCIe protocols, specifically Gen5 or Gen6. This is a technical leadership position requiring strong analytical and debugging capabilities.
TAL's take
Solid technical role at an established engineering firm with clear requirements, though scope is specific to legacy/service-based verification.
Very clear scope focused on VLSI verification with specific protocol and YOE requirements.
Salaries at Ust
20.9 LPA average
Based on 19 Grapevine salary entries for Ust.
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Must haves
- 5-8 years of design verification experience
- Complete verification lifecycle knowledge
- Strong hands-on experience in SystemVerilog and UVM
- Minimum 1 year of hands-on experience in PCIe Gen5 or Gen6
- Expertise in UVM testbench and component development from scratch
Tools and skills
About the company
Global IT services and product engineering firm, established mid-tier status.
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