MODULE LEAD - FPGA design techniques
Happiest Minds Technologies is hiring a senior FPGA Design Engineer to develop and verify FPGA-based solutions. The role involves managing the full design flow from RTL synthesis to place-and-route and timing closure. Candidates will perform hardware debugging in lab environments and collaborate on system integration. Proficiency in Verilog/VHDL and FPGA toolchains is required.
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Experience
5-8 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Happiest Minds Technologies is hiring a senior FPGA Design Engineer to develop and verify FPGA-based solutions. The role involves managing the full design flow from RTL synthesis to place-and-route and timing closure. Candidates will perform hardware debugging in lab environments and collaborate on system integration. Proficiency in Verilog/VHDL and FPGA toolchains is required.
TAL's take
Solid role at an established mid-tier firm with well-defined technical scope.
Highly specific technical requirements for FPGA design flow and hardware validation.
Salaries at Happiest Minds Technologies
39.5 LPA average
Based on 2 Grapevine salary entries for Happiest Minds Technologies.
Other roles
10 - 12 years
33 LPA average
Range: 33 - 33 LPA
Other roles
18 - 20 years
46 LPA average
Range: 46 - 46 LPA
Must haves
- 5-8 years hands-on FPGA development experience
- Proficiency in RTL design using Verilog or VHDL
- Experience with synthesis and implementation tools like Libero, Vivado, or Quartus
- Hands-on experience with Tcl scripting
- Strong hardware debugging skills using oscilloscopes and analyzers
Tools and skills
Nice to have: sdi, displayport, hdmi 2.2, slvs, motor control, holoscan, tsn, ethernet, lint, cdc, spirent, ai agents, prompt engineering.
About the company
Established IT services and digital transformation company.
Posts mentioning Happiest Minds Technologies
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