Full-Chip STA Engineer
Proxelera is hiring a Full-Chip Static Timing Analysis Engineer for their semiconductor team in Hyderabad. The role involves managing full-chip timing analysis, constraint development, and optimization across various design stages. Candidates must have expertise in STA sign-off, Synopsys PrimeTime, and scripting languages like TCL or Perl. The position requires strong debugging skills and a solid understanding of VLSI design methodologies.
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Experience
3-6 years
Function
Engineering
Work mode
Onsite, India
Company
Tier 2
What you will work on
Proxelera is hiring a Full-Chip Static Timing Analysis Engineer for their semiconductor team in Hyderabad. The role involves managing full-chip timing analysis, constraint development, and optimization across various design stages. Candidates must have expertise in STA sign-off, Synopsys PrimeTime, and scripting languages like TCL or Perl. The position requires strong debugging skills and a solid understanding of VLSI design methodologies.
TAL's take
Defined IC role in a niche engineering domain, standard mid-tier assessment.
Highly specific technical requirements and responsibilities for a specialized VLSI role.
Must haves
- Strong knowledge of STA concepts and timing sign-off methodology
- Hands-on experience with Synopsys PrimeTime
- Proficiency in TCL, Perl, or Shell scripting
- Experience in SDC constraints, MCMM, and Timing ECO
- Understanding of OCV/AOCV/POCV concepts
Tools and skills
Nice to have: tempus, 7nm, 5nm, 3nm.
About the company
unfamiliar company, default mid-tier